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```PDP-1 COMPUTER

EIECTRIGAL ENGINEERIICf DEPARTI^NT

mSSACHUSETTS INSTITUTE (F TECHNOLOGY

CAMBRIDGE, MASSACHUSETTS

02139

/^^^

PDP-35

INSTRUCTION MANUAL
PART 1 — BASIC INSTRUCTIONS

(j^^ fa^ ONf ^ ^^^^'

21 March 1972

1.

Basic Instructions
Word FornBts

Each PDP-1 word is 18 bits long. The hits are numhered, in
deciiml^ to 17 from left to right. In this manual, all numbers
are octal, unless otherwise specified. The numbering of bit
positions in words is always decimal.

1 2 S 4 S 6 7 8 Q 10 11 12 1^ 14 IS 16 17

i

first
octal digit

last
octal dioiit

1.1.1

Number Forrrats

The entire word may be regarded as a signed 18-bit number.
Bit is the sign bit. It is on (i.e., a "1'*) if the number is
negative. There are two different ways (called one* s complement
and two's complement) in which the PDP-1 hardware can interpret
signed numbers. Positive numbers are the same in both representa-
tions. Positive numbers are represented in the ordinary biriary
notation. The range of positive numbers that can be represented
is to 377777 (13107I decimal).

In ones* s complement, the negative of a number is formed by
complementing all of its bits. Hence -1 is represented as 777776
in one's complement. 400000 (-I3IO7I decimal) is the most
regative number that can be represented in one's complement. Note
that there is a representation for -0, 777777- Since -0 and +0
are similar in their arithmetic properties, this dual representa-
tion is an ambiguity which can be the source of difficulties.

In two's complement, the negative of a number is formed by
compleriBnting all bits of the number and then addins 1. Hence -1
is represented as 777777* 400000 (-I3IO72 decimal] is the most
negative number that can be represented in two's complement. Note

that the negative of is 777777+I which is
complement notation, is represented uniquely.

0.

In two' s

Number ("base lo) One's Complement Tv/o' s Complement

-0

5

-5
131071
-131 071
-13 1072

777777

5
777772
377777

400000
no representation

no representation

5
777773
377777

400001

400000

By ignoring the sign convention, a program could deal with
(^ta words as unsigned numbers ranging between and 262143
(decimal) or and 777777 (octal).

The one' s complement addition rule for 2 18-bit numbers is
as follows. Add the 2 numbers in the normal fashion, propagating
carries to the left. If there is a carry out of the last bit (bit
0) add this carry in at the right hand side of the word (bit 17)^
The addition is said to overflow if the result does not correctly
represent the algebraically correct sum, i.e», the magnitude of
the correct result is greater than 377777-

numbers in the normal fashion, propagating carries to the left.

Ignore any carry out of bit 0, Overflow is said to occur if both
operands are of the same sign and the sign of the result differs
from the signs of the operands.

In both one's and two's complement, the overflow condition
is equivalent to the condition that a carry occurred from bit 1
but not from bit or vice versa.

Example

One's Complement

Two's Complement

7

+ -100
-61'

7
+ 777677
777705"

7
+ 777700
/77707

123456

+ 666666

1012344

123456
+ 666666
1012344 =

012345

123456
+ 666666
1012344 =

= 012344

A ^

^(

1 2 3 4 5 ' 6 7 8 9 10 11 12 13 14 15 16 1?

G C C

G

G I

:aaaaaaaaaaaa

t

1 >k L J

V

Op. Code

V

1 of 4096 (decimal) locations

the ''i" bit

The "instruction part'' consists of 5 bits (the "op, code^' )
that tell which instruction the computer will do if it executes
this word, and the '^i-bit" which has to do with address
modification.

Except for imp, and ,1s p , addressable instructions take a
minimum of two memory cycles — one to fetch the acti:&l
instruction and another to fetch the operand. .Imp and ,1s to do not
take an operand and consequently, require a minimum of one cycle.
The amount of time required for the execution of an addressable
instruction depends on what addressing is done (see PDP-35,
INSTRUCTION mNIJAL, Part 2 for complete information). Under the
most common conditions, the actual time required for instruction
execution is the minimum time given above.

1.1.6

1 2 3 4 5 67 8 9 10 11 12 13 14 15 16 17

CGGGCEEEEESE E E E E S Ej

^

Op. Code

JL

•V

Extended Op. Code

Tne low 13 bits are actually an extension of the op. code,

further specifying what the computer is to do. Non-addressable
instructions never require more than one cycle because they do
not reference memory, except for the ivk instruction with PRL on
(See PDP-35, INSTRUCTION mNUAL, Part 5).

1.2 Registers

The PDP-1 contains 6 18-blt registers which define the state
of the user*s process. They are the A (accumulator), I
(input/output register), X (index register), G, F (flag regis-
ter), and W, When the user first logs in, all of these registers
contain (all hits off). This defines the initial state of the
user's process. Each of these registers has its own properties,

1.2.1 Accumulator

The accumulator is the major register for use in processing
^ta. Most arithmetic and logical instructions operate on data in
A and leave results in A.

1.2.2 Input /Output Register

The input/output register was origin lly used primarily for
input/output operations. This is no longer true. I is now a
secondary accumulator, jv^ny arithmetic and logical operations can
"be performed on data contained in I.

1.2.3 Index Register

The index register has two functions. First, it is used in
addressing memory (See PDP-35, INSTRUCTION mNUAL, Part 2),
Second, it is, like I, a secondary accumulator.

1.2.4 G Register

The G register contains the l5-hit program counter, the
overflow hit, the extend mode bit, and the arithmetic mode hit.

The program counter (PC) is bits 3-17 of" the G register. The
purpose of the program counter is to tell the processor where in
memory the instruction that is to be executed next lies. The
program counter is incremented after each instruction so that
instructions are executed sequentially, according to their loca-
tions in memory. When the program counter is incremented, carries
out of bit 6 of G are lost. Thus, the instruction executed after
the instruction in location 7777 is the instruction in location
0. Certain testing instructions increment the PC an extra time,
causing an instruction to be skipped.

Bit of G is the overflow bit (CFF ). It is set to 1 by
certain arithmetic instructions when overflow occurs, and cleared
by the szo instruction. Bit 1 of G is the extend mode bit (EXD),
This bit is used in addressing (See PDP-35^ INSTRUCTION mNUAL,
mrt 2), Bit 2 of G is the arithmetic mode bit (tWOS). If this
bit is off, the processor is in one's complement modef if this
bit it on, the processor is in two's complement mode.

The f orraat of the G register is shown below.

12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

E

T

p

P

P

P

P

p

P P

p

P

P

P

P

P

P

V

X

W

c

c

c

c

G

c

G C

G

G

G

G

G

G

G

F

D

3

4

5

6

7

8

9 1

1

1

1

1

1

1

1

-- ■

s

1

2

3

4

5

6

7

1,2.5

Plag Register

The flag register contains the 6 program flags and several
bits which define various states of the processor.

The program flags are 6 1-bit registers that may be quickly
and conveniently set and tested by programs (see Operate and Skip
class instructions'}:; Ako jee p<"-f 2*Z»(<t ^ He ^'^^ ^^'^

The 3 bits AMD, AEF, and AAL determine the mode of
addressing which the processor will use on memory referencing
instructions (see PDP-35, INSTRUCTION mNUAL, Part 2).

The 2 bits SBH (Sequence Break Hold) and SBM (Sequence Break
r/bde ) determine the sTate of tlTe sequence break sysTem (see "T^DP-
3B, INSTRUCTION MANUAL, Part 3).

The ESI (gcecute Swingle I^nstruction) bit causes the proces-
sor to trap aFter each instruction is executed (see PDP-35^
INSTRUCTION mNUAL, Part 5).

The PRL (Program Reference List) bit affects the way in
which the ivk (invoke) instruction works (see PDP-35> INSTRUCTION
MANUAL, part 5). When the PRL bit is 1, references to memory
locations 0-77 ^^Q illegal.

The format of the F register is as follows f

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

A

A

A

S

S

P

E

P

P

P

P

P

P,

M

E

A

B

B

R

S

.

F-

F

F

F

F

F

D

F

L

M

H

L

I

1

2

3

4

5

6

1.2.6

W Register

The W register, a software register maintained by the time-
sharing supervisor, is used solely for communication with the
supervisor. Certain mta and ivk instructions (both are supervisor
calls) use the W register (see PDP-35, INSTRUCTION mNU^L, Part
5).

1,3

Instructions to Set the Arithmetic r4ode

The PDP-1 processor .may operate in either of tv/o arithmetic
modes, one's complement and two's complement. The arithmetic mode
In which an instruction is executed is determined by the state of
the TWOS bit in the G register. When the TWOS bit is off

i5/

(contains a o), the processor is in one's complement mode. One's
conplement mode (TWOS off) is the default mode. The following
instructions change the state of TWOS,

?^emonic Op .Code Name Function

^m 770060 Enter two's mode Set TWOS to 1

elm 77006! Enter one's mode Set TWOS to

The instructions add , a dm, sub , mul , d4v, idx^ , isp, sf t ,
opr , and opr i (the micro-program instruction) behave differently
in one's and two's mode. Address arithmetic is always done in the
current arithmetic mode.

1.4

In this section, the symbol '"V"* i^sed in the context of ^^Ins.
y" means the memory location referenced by the instruction '^insj*.
The notation ^^ {jj*' means the contents of location y. For
information on how addresses are computed, see PDP-35^ INSTRUC-
TION mNUAL, Part 2.

Data Moving Instructions

These instructions serve to move data betvjeen memory loca-
tions and the A, I, and X registers. These instructions copy data
words (or parts of words) from one place to the other and never
destroy inf orimtion at the source.

Mnemonic Op. Code Name

3^c y

20

Ic^d A

lio y

22

Ijcr y

12

dac y

24

deposit

A

dio y

32

deposit

I

dap y

26

deposit
part of

A

dip y

30

deposit instruc-
tion part (of A )

d2m y

34

deposit
memory

zero in

Function
Copy (y) into A
Copy (y) into I
Copy (y) into X
Copy A into y
Copy I into y

Copy the low 12 bits of A

into y. The high 6 bits of
y are unchanged

Copy the high 6 bits of A
into y. The low 12 bits of
y are unchanged

ly^kes location y contain OC^

1.4.2

Logical Instructions

These instructions take one operand in A and the other from
a memory location. The result is left in A, Each bit of the
result depends only on the corresponding hits of A and the memory
word before the operation.

Each bit of A will be a 1
if and only if the corres-
ponding bits in A (before
the instruction) and (y)

Miemonic

Op.

Code

Name

were —

and y

02

and

both one

ior y

04

inclusive
or

not both zero

xor y

06

exclusive
or

different

1,4.3

Arithmetic Instructions

The following instructions are used to compute sums and
differences. The ^left'^ operand is in A and the ""right** operand
is taken from memory. The result is left in A and in the case of
arim (add to memory), it replaces the contents of the memory
location as well.

In one^ s mode, arithmetic is done in one's complement. If
the result of an operation is -0, it is changed to +0 with the
exception that (~0j - (+o) results in -0.

In two's mode, arithmetic is done in two's complement.

The overflow bit GIF will be set by the add, adm, or sub
instructions if the signed result cannot be correctly represented
in 18 bits. This is the case if and only if a carry occurred from
bit one and no carry occurred from bit 0, or vice versa. See the
szo instruction.

r*(hemonic Op. Code Name

sub y 42 subtract

Function

Sum of A and (y) to A

Sum of A and (y) to A and y

A minus (y ) to A

1.4.4

Multiply and Divide

Multiply and divide behave very differently in one* s mode
and two's mode. Hence the actions of these these instructions
will be explained separately for each of the arithmetic modes.

Mnemonic Op. Code JNiarae
mul y 54 multiply

div y 56 divide

Function

A times (y) to A, I . \

Quotient of (^FCy) to A
Remainder to I
Skip if the quotient does
not overflow

Multiply takes a minimum of two memory cycles plus from 3 to
15 microseconds, depending on the number of one* s in A. Divide
instructions which skip take two cycles plus 20 microseconds. In
one's mode, divide instructions which do not skip take 2 cycles, -,^-v^^
In two's mode, divide instructions which restore A and I and do /y^

not skip take 2 cycles? other non-skipping divides take 2 cycles | • f
plus 20 microseconds.

1.4.4,1 Multiply (One's Complement Mode)

Multiply and divide deal with double-length numbers, mul xmj

be viewed as multiplying two I7~bit integers plus signs to
produce a 34 bit integer plus two signs. A result of -0 is
changed to +0.

Result of Multiply (One's Mode)

12

'ign-£

• • •

16 17 1 2 16 17

[ | I I I* * ♦! |~*-j -~same as sign

I t

least significant bit

Quite often, two integers are multiplied such that the
result can be held in one register. In this case, A will be +0 or
-0, and the result will be in I. but it will appear to be shifted
left one bit position. A rlr is instruction will convert I back

to normal single-length integer format.

Examples —

Before mul

After

mul

A y

A

I

3 200000

1

400000

-3 200000
3 2

777776

377777
14

-0 anything

1,4.4.2 Multiply (two's Complement Mocie )

Multiply and divlcJe deal with d ouble -length numbers • mul may
be viewed sS multiplying two 17 bit integers plus signs to produce
a 35 bit integer plus sign in the combined A and I registers.

sign'

12 16 17

12 16 17

— — -• • • •

• • •

a

t

least significant bit

When two integers are multiplied such that the result can be

held in one register, the entire result will be in I in the
conventional signed integer f orrrat.

Examples —

Before

mul

After

mul

A

y

A

I

3

-3
3

-3

400000
400000

200000
200000

2

2

2
400000

777777

777777
777777

200000

600000
200000
6

777772

1.4,4.3 Divide (One's and Two's Mode)

Divide (div ) takes a double -length integer in A and I (in
the format produced by mul in the same arithmetic mode) and
divides this by a single length integer in the addressed memory
location. The result of a div is a single-length integer quotient
in A^ and a single-length integer remainder in I. The sign of the
remainder will be the same as that of the dividend.

If a quotient overflow occurs, that is, if the divisor goes
into the dividend more times than can be represented in the
accumulator (a), the div instruction will not skip. In one's
mode, a divide will skip if the absolute value of the original A
is less than the absolute value of the divisor. In one's mode if
a div does not skip, the original A and I are preserved, except
that if A and I were both -0, A is changed to +0. In two's mode,
if Q- div does not skip, the contents of the A and I registers are
preserved if the divisor is 0, otherwise they are us-uetlly
destroyed, div never sets the overflow bit.

Examples

Before divide

After divide

One' s

Mod

e

Two' s

Mode

A

I

C(Y)

A

I

A

I

16

2

3

1

7

7

3

1

2

1

11

777773

-1

-1

4

25

777774

-3

1

-5

1

1

400000

200000

3

6

YYYY76

377777

777774

200000

300000

-1

777777

400000

1

2

200000

400000

577777

200000

400000

6

777776

no skip.

A

and

no skip.

A and

I unchanged

I unchanged

100000

222222

100000

no skip.

A

and

no skip.

A and

I unchangt

-d

I destroyed

1.4.5

Counting Instructions

The two instructions irix and isp , add one (in the current
arithmetic mode) to the contents of the specified meraor;^'" location
and leave the result both in memory and A, iso skips the next
instruction if the result is positive. Including 0* Neither
instruction will set overflow. In one's mode, a -0 result is
corrected to +0, i.e., indexing -1 results in +0, and indexing -0
results in +1.

I^hemonic Op. Code Name
Idx y 44 index

isp y 46

Function
(y) + 1 to

A and y

index and skip (y) + 1 to A and y

if result positive skip if result ^

1.4.6

Compare Instructions

The following two instructions are used to compare A with
the contents of a memory loction. The comparison is done bit-by-
bit, therefore, the contents of A are the same as the contents of
memory if and only if every bit of A is the same as the
corresponding bit in memory.

Mnemonic Op. Code Name and Function
sas y 52

50

skip if A is the same as (equal to) the
contents of y

skip if A is different from (y)

1.4.7

Transfer of Control

All of the following instructions have the effect of
changing the program counter (PC) so that the PDP~1 will begin
executing instructions out of the nornp. - ! sequence.

jvhemonic Cfp.Code Name

jump

jmp y
Jdp y
jsp y
Jda y
cal y

60
14
62

17

16

Function

transfer control to location

y

program counter

program counter

Jump and deposit store A in y, save G in A.

accumulator Jump i:o y+1 (dac y, Jsp y+l)

call

store A in OOiOO, save G in
(similar to Jda lOO)

The instructions .1dp , .1s p, and Jda are used chiefly for

calling subroutines. The saved G register is the linkage
which it was called.

Simple Examples

Jdp subr

Jsp subr

Jda subr

subr,

Jmp i subr

subr, dap subx

s ubK , Jmp

subr,

dap subK
• « •

subx, Jmp

These examples show three ways in which a subroutine imy be
called. In each example the method by which the subroutine
returns to the calling program is illustrated. In each example
the return is to the location immediately following the subrou-
tine call.

1.4,8

Execute

The xct instruction causes the contents of the specified
memory location to be executed as an instruction. xct * s may
execute other xct' s. In all cases the effect is the same as if
the xct were replaced by the instruction it addresses, xct. takes
a minimum of one cycle plus the time to do the addressed
instruction.

Mne mon ic Op . C od e Na me
xct y 10 execute

Function

execute the contents of y as
an instruction

1,5 Mon-Memor^T- Referencing Instructions

1.5.1 Skip Class

Instructions from the skip class will cause the PDP-1 to
Junro over one instruction in the normal sequence if the skip
conciition described by the lov/ 13 bits of the instruction is

true.

A skip class instruction has the following format —

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

IIOIOISSSSSSSSSSSS

V

■^ /N^

Op, Code 64=skp

V

skip conditions

invert sense of skip

Each of the low 12 bits enables a different skip condition.

r%iemoniG Op. Code

skp 640000

szf n 64000n

szs nO 6400nO

Name

skip

skip on zero
flag n (l<n^7)

skip on zero
switch n {^<n<j)

sza

640100

skip on zero A

spa

64oeoo

skip on positive A

sma

64o4oo

skip on minus A

szo

641000

skip on zero
overflow

spi 642000

sni 644000

skip on positive I
skip on nonzero I

Function

never skips

skip if program flag n is ^>
off. szf 7 skips if all->
flags are off.

skip if sense switch n is
off. szs 70 skips if all
switches are off.

skip if A (0-17) =

skip if A (0) =0

skip if A(0) =1

skip if the overflow bit
{OTF ) is off.

A szo instruction always
clears OTF

skip if 1(0) =
skip if 1(0-17) +

If more than one skip condition is enabled, the instruction
skips if any (i.e. the logical OR) of the skip conditions is
true.

The "i-bit" reverses the sense of the skip, i.e., a skip
instruction vjith the "i-bit" on will skip if and only if the
corresponding instruction with the "i-bit" off would not skip.
For example, slcp 4200 will skip if either I 4 o^ A(o) = 0. skp
i 4200 will not skip if either of these conditions is true. Thus,
skp i 4200 will skip only if I = and A(o) = 1.

The following mnemonics define several useful compound skip
instructions, i.e, each has several skip conditions enabled.

lyhemonic Op. Code' Name

szm

spq
clo

640500 skip on zero or

minus accumulator

650500 skip on positive
quantity

65I6OO clear overflov;

Function

skip if A (0-17) = or if „
A(o) = 1
(szm = smaVsza)

skip if A >
(spq. = srraVsza i)

this never skips f it is
used to clear overflow
(clo = spaVsmaVszo i)

1.5.2

Shift/Rotate Class

The shift/rotate instruction class is markedly different in
one's mode and two's mode. A separate explanation of the
shift/rotate instructions is given for each arithmetic mode.

1.5.2,1 One's Complement Mode

Shift is an arithmetic operation. Shifting a number left one
hit position is equivalent to multiplying it by two, A single
right shift divides a number by two. The sign bit does not change
during a shift because the sign of the result must be the same as
that of the operand. The sign bit is copied into the bit vacated
by the shift.

Rotate is a logical operation in which the register being
rotated is considered to be a ring with bits leaving one end and
coming back into the other.

The shift/rotate class may operate on either A or I or both
combined as a double-length register. In the case of a combined
(Ai) shift, the sign of the accumulator is taken as the sign of

the whole 36-bit number. No shift/rotate instruction will set
overflow.

The number of bit positions of shift or rotate is determined
by how many of the low nine bits of the instruction are on. Thus,
ral 1 , ral 2 , and ral 400 are equivalent.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

1 1 1 l|R|Sh|l|A[S S S S

V

A /N

Op. Code 66=sft

right or left

t t' V

I A one bit for each shift

-both for combined shift/rotate

shift or rotate

ivhemonic

Op ,0 0(1'

sft

660000

sal

665000

sar

675000

ral

651000

rar

671000

sil

666000

sir

676000

ril

662000

rir

672000

sol

667000

scr

677000

rcl

663000

per

673000

Is

1

2s

3

3s

7

4s

17

5s

37

6s

77

7s

17V

8s

377

9s

777

Name and Function

shift A left
shift A right
rotate A left
rotate A right

shift I left
shift I right
rotate I left
rotate I right

shift combined A I left
shift combined AJ right
rotate combined A I left
rotate combined A I right

Used in conjunction with
the above to shift or
rotate the indicated
number of places

1,5.2.2 Two* s Complement Mode

The two's complement mode shift instruction offers a very
powerful set of operations including rotates, logical and arith-
metic shifts, normalization, and bit counting. The register
operated upon may he the A, I, A I (hit ±7 of A joined to hit of
l), or lA (hit 1? of I joined to hit of A). The A and I
registers may he operated upon independently.

1 2 3 ^ 5 6 7 8 9 10 11 12 13 14 15 16 17

liOli|AAAAlIIIC

C G C

C

I -11 . >y i\_

,>

op. Code 66=sft ^ ^

A field I field

V

Count

The 4 hits of the A and I fields are interpreted as follows!

D R R R

Of

If

2f

3f
4f
5r
6f

7f

D = directionf => right 1 => left
RRR = operation! decoded as follows f

If direction = right, do nothing to this register,'
If direction = left, zeroes are shifted into hit 17;>
hit is unchangedf if hit lost from hit 1 =1= hit 0, set
overflow (arithmetic shift left).

If direction = right, see helow.

If direction = left, hit of opposite register is

shifted into hit 17^ hit is unchanged! if hit lost

from hit 1 =f hit 0, set overflow (arithmetic shift left

comhined).

Shift zeroes into vacated hit (logical shift).

Shift ones into vacated hit.

Shift hit of this register into vacated hit.

Shift hit 17 of this register into vacated hit.

Shift hit of opposite register into vacated hit.

Shift hit 17 of opposite register into vacated hit.

T/i£ myttymoy,;^^ J^or 2\$ ^^ojiz \$4)"-pt I'^^^f^ooh^o^S' ^/"e

cj.<^Y

where' '*^''^r'^>'>c ^,r

5

?

^

2

uj UV

fa-i) w.'^"^''^

Ones
8

V

s

2.
3

Cj " if ''

Ot^^'ni 2.0

6<^/\A^ ftM ^c<(31

If A field = 01, them

If the I field is 00, 10, or 11, then shift I until
either l(o) ^ l(l) or the count runs out. A will
contain the number of places shifted (Norimlize ).

If the I field is not 00, 10, or 11, then I will shift
as usual. A will contain the number of ones shifted out
of 1(17) (Count Bits).

Notet A is first cleared and then counts during the
operation, hence I field = 11 will shift in zeroes just
as I field =10 does.

I field = Ol is reserved for future expansion.

The number of positions to move the selected regis ter(s) is
determined by the number in the 5 hit count field. If the count
field is 0, the count is taken from X (IS-I?)*

Execution time = 1 cycle + (count~5)x0.2 microsecond

USAGE

ID and the assembler consider certain symbols consisting
entire ly of upper case letters to be two*s mode slilft instruc-

'any expression, e.g., storage word, constant, etc. When typin
into ID, the instruction must be preceeded by a single quote ('

in ~t

All of the common operations possible with this instruction
can be specified by a 2 , 3 , or 4 letter symbol.

The symbols specifying shift/rotate operations are formed as
f ollowsf

"ehlrt

<direction f ie Id X ^^ og io t or f i Q.l d X ^ * ^ ^ l-*^ l^hi f ield>

<direction f ield>

The direction field indicates the direction in which
the selected register is to be moved. The only
permissable contents of this field are R or L, specify-
ing right and left motion, respectively.

CHai^ G>£D

6HA^^^^c>

<%gister f leld>

The register field selects the register which is to be
operated upon. The register field may contain either an
A, I, C, R, or N.

.ndicates the A register.

I indicates the I register,

G indic^es the combined A and I registers (Al). In
this models, bit 1? of A is joined to bit of I,

R indicates >^e reverse combined I and A registers

(ia). In this mode, bit 1? of I is Joined to bit of

A.

N indicates that th^^pperation to be performed is a
normalize or count bits^^eration (A field = Ol). LNS
indicates that I is to besnorimlized, i.e., I is to be
shifted left until l(o) 4 1*^) ^^ "the count runs out.
The number of positions shifte>^will be placed in A. if
the symbol is not LNS , then ^^ operation is count
bits. I is the selected register and is moved as
specified by the count, <direction field >, and <shift-
in field>. The number of ones shifted out of l(l7) is
placed in A .

<shift-in f ield>

The shift-in field determines what is to be shifted
into the bit position that is vacated as the selected
register is moved. This field may be blank or it may
contain one of the symbols Z, 0, L, H, OL, OH, or S.

If the shift-in field is empty, a rotate is assumed (a
rotate is an operation where the bits shifted out of
one end of the register are shifted into the other end
of the register).

Z indicates that zeroes are to be shifted in.

indicates that ones are to be shifted in.

L indicates that the low bit of this register is to be
shifted in. In the case of double register operations
(register field = C or r), the low bit is the least
significant bit of the entire 36-bit register.

H indicates that the high bit of the selected register
is to be shifted in. In the case of double register
operations, the high bit is the most significant bit of
the entire 36-bit register.

C^f^j\/Cp^C>

OL indicates the the least significant loit of the non-
selected register is to "be shifted in. In the case of
double register operations, this bit is taken to be the
least significant bit of the most significant register.

OH indicates that the most significant bit of the non-
selected register is to be shifted in. In the case of
double register operations, this bit is taken to be the
most significant bit of the least significant register.

S indicates that the operation is an arithmetic shift.
The selected register is shifted arithmetically. Note
that an arithmetic shift is equivalent to a multiplica-
tion or division by a power of 2, During an arithmetic
right shift, sign bits are moved into the vacated bit
position^ during an arithmetic left shift, zeroes are
moved into the vacated bit position. If any significant
bits are shifted out during a left shift, overflow is
set (shifting out a significant bit will change the
sign bit).

EXA.MPIES

OPERATION A I A I lA

shift left
shift right
rotate left
rotate right
logical left
logical right

count bits in I
norrralize I

Two rotate/shift operations, one moving only A and the other

only I may be combined into one instruction by logically ORing

together the Instruction moving A and that moving I. Both ORed
instructions must share the same count.

EXAMPLES

shift A right 3? shift I left 3 RASVLIS 3

rotate A left 7? shift I right 7 lAVRIS 7

copy reversed bits of I into A lAOLVRI 18.

clear A and I RIZVRAZ 18.

reverse 36 bits of A I lAOIVRIOH 18.

IAS

LIS

ICS

IRS

RAS

RIS

RCS

RRS

lA or LAH

LI or LIH

LG or LCH

IR or LRH

RA or RAL

RI or RIL

RC or RCL

RR or RRL

lAZ

LIZ

LCZ

IRZ

RAZ

RIZ

RCZ

RRZ

RN 18.

LNS 17.

1.5.3 The law Instruction

law and law 1 ('^load accumulator with") nrnke it possible to
load the accumulator with 12 bit positive or negative numbers in
one cycle.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

11100|l|NNNNNNNNNNNNl

V ' ^^

V

12 -bit number to be loaded

Op. Code 70=law

on to complement

law first loads A from the address part of the instruction and
then, if the i-bit is on, complements A. Thus, law 3 puts three
into A and law i 3 puts 777774 into A.

In one's complement mode, law i n (where 0<n;^7777) will put -n
(one*s complement) into A.

For convenience when programming for two's complement mode,
Ian ("load accumulator with negative'*) is defined as law 7777 *
Thus, Ian n (l :^ n ^ lOOOO) will load A with -n (two's
corapleriBnt }.

1.5.4

The Operate Class

Each bit of the address part of an opr instruction enables an
operation in the processor.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

lOJSEEEEEEEEEEEl

^ ^ — ,, — , — . >

1111

V

— — — ^ — ^ ^%^

V

Op .Code 76 = opr ^ -^ Operation enabling bits

<VA.V^

Several operations can be enabled by turning on more than one
bit in the address part. The order in which the various
operations on A and I occur is — f irt, clear A and clear Ij
Sifl ond , complement and step A j thiia^ ^ OR in the test wordf
fourth, complement A and complement jif and last, switch data

between A and I.

^ttonJl

Miemonic
opr
nop
stf n

Op. Code
760000
760000
7600ln

76000n

760200
762000
762200

Name

no operation

set flag n
(lln^7 )

clear flag n

clear A

OR test word to A

complement A

Function

one cycle time delay

set one of the sIk program
flags. Set all if n=7. Set
none if n=0

clear selected flag. Clear
all if n=7. Clear none if
n=0

put into A

copy test
into A

word switches

76IOOO

76I20O clear and

complement A

764000 clear I tmmt^k^^^f/^

put mill in A
put into I

760100
76004

7 6 00 4

complement I

/\

A

V lla 760020 load I from A

vr

swp 760060 swap A and 1

^

csa 760^00 complement and complement A, then add one

step A to A, U #^r*s f^oJ^^ l^-f A

fifi / _jjaV 1 1 III II f I 1 run A. "^7^^- i4 ^^^ '^odt^^A ^^*if;^j

Although the stf and elf Instructions are usually used to *<j/
nanipulate the program flags, there are also the following two
instructions — -^

Mnemonic Op .code Name Function

^
^
^

^
^

Ipf 770051 load program flags Top 2 bits of I to Address ^

mode bits. Bottom 6 bits _^

of I to program flags.

^

of I. Flags to low 6 bits }{

of I. --V

1.5 • 7 The Micro-program Class

The micro-program instruction class has the following instruc-
tion f orimt —

1 2 3 4 3 6 7 8 9 10 11 12 13 14 15 16 ±7

1 1 1 1 1 ixx[yyy|a a a[s s s"s1

L

-"V

Op .Code 77

^^-^^' — V — ^' — V — ^^

operands (column in
following table)

t ski

— S/

p conditions

assignment of result
operation (row in following table)

YYY
000

Oil

Symbolic Specification of Micro-program Operations

XX 00

I

N

s s

P T
001 ] E R

C U

I G

010 j A T

L I

N
S

110

111

SA

(a)+i

SI
(I)-^l

I (x1+i

01

10

11

TI

NI

TA

m

A-^I

(I)

X-5A
(A)

AMI xm

1

100 j (zero) j AVI
101

XVA

IX

MX

X->I
(I)

T (Test, or transfer)

N (Negate)

exchange (see

explanation below)

XMI ! M (arithmetic minus)

XVI 1 V (inclusive or)

{ A~I

AM I XAA I XAI ! A (bitwise and)

! J

! 1 1

! "' (exclusive or)

1

+ (arithmetic plus )

X'^A

X~I

A+I

,-y\

x+i

S (Step^ i.e. J add one)

The
fields

AAA

functions of the result assignment and
-re as follows —

Bit 11=1 will put the result in A
Bit 12 =d. "^ ''^ "• "^ "' I
Bit 13=1 '• " " "^ "' X

skip condition

ssss

Mode
Bit l4=dt Skip if the result is
Bit 15=1 f '^ '* "' '* "^

Bit 16=1 f '' "^ '^ "^

Bit I7=^t '* "^ "' "■

fi»

One* J
>

< -0
=
= -0

Two* s
>

= -1

The execution of a micro-program instruction computes the
result specified by the XX and YYY bits (i.e. from the Table on
the previous page), puts this result in the specified register (s)
if any, and skips if any of the specified conditions are true.
Note that the skip condition is evaluated on the result of the
micro- program, not the final contents of any given register, and
the result need not be assigned to any register. Thus, it is
possible to test the sum of A and I to see if it is greater than
without destroying the contents of these registers. The
instruction to do this is 773610, or symbolically, A+I>, All

micro-program instructions require one cycle.

The "t"- operation clears the transmitted register after the
transfer. This may be circumvented by assigning the result back
to the transmitted register. See the examples •

The exchange operation is a special case. The result A-»I (l)

iTBans that the result of the function is the old I register, but
in addition the accumulator is placed in I. This secondary

assignment is done before the assignment given by the AAA bits in
the instruction. Thus, the instruction A->I (772400 ) will move A
to I, A->IA (772500) will sv/ap A and I, and A-»II (772440 ) does
nothing (because the prinary assignment is to I and the result is
the old l).

The add, subtract, step, and negate operations vary according

to the arithmetic mode. In one's mode, negate produces the

complement of the specified register. In two's mode, it produces
the complement plus one.

In one's mode, arithmetic results (from add, subtract, negate,
and step) of -0 are converted to +0, except in the following
casesf

(-0) + (-0) = (-0)

(-0) - (+0) = (-0)

- (+0) = (-0)

Micro-program instructions executed in one* s mode never turn

on the overflow bit. In two* s mode^ the instructions add and

subtract will turn on the overflow bit if the addition or

subtraction overflows. Stepping 377777 ^nd negating 400000 also
set overflow in tv;o*s mode.

USAGE

The assembler considers certain symbols consisting of capital
letters as micro-program instructions. The entire instruction
must be in upper case, and nay appear in any expression, e.g.,
storage word, constant, etc. When typing into ID, the instruction
must be preceded by a single quote I' ).

Micro-program instructions are specified by concatenating
three "fields" — the result field, the assignment field, and the
skip field. The characters in all of these must be in upper case
and there must be no separator between the fields.

<result f ieldX^ssignment f ieldXskip f ield>

<result field>

The result field must be one of the twenty-
eight results given in the table on a previ-
ous page. '*C"' nay be used in place of "°n"'
(negate ).

<assignment f ield>

<skip f ield>

The assignment field may be null (no char-
acters) QT any combination of A, I, and X to
specify in which registers the result will be
placed.

The skip field may be null or contain any
combination of <, >, P, M, |, _, and =. Note
that the <, =, and ^are treated differently
depending on the arithmetic mode.

Symbol Meaning! One's Two's

>

P
M
<

<M

skip

if

result

>o

>o

skip

If

result

=+0

=0

skip

if

result

=-0

=-1

skip

if

result

<-0

<o

skip

if

result

=+0,:

=-0

=0

skip

if

result

=+0,:

=-0

=0

skip

if

result

<-0

<-l

invert the specified skip conditions

Since the octal representation of a micro-program instruction
is computed by exclusive-or' ing all of the specifications within
each field, redundant specifications rray lead to unexpected
results. For example, TAIII and TAI» are the same as TAI.

SAMPLE MICRO-PROGRAM INSTRUCTIONS

The following are the same in One* s and Two's Mode.

symbolic octal action

A+I 773600 ■ computes sum of A and I and does nothing at

all with it.

A+IA 773700 the sum of A and I is put into A.

A+IAIX 773760 the sum of A and I is put into A, I;, and X.

ZAIK 77II6O A, I, and X are cleared.

SA> 771210 skip if A plus one is > 0.

SAAP 771302 add one to (step) A and skip if it is 0.

TXM 776001 skip if X is 777777 and clear X.

TXXM 776021 skip if X is 777777-

TAXI 774060 transfer the contents of A into I and X, then

clear A,

TAAXI 774160 same as TAXI, but A is not cleared.

A->IA 772500 exchange the contents of A and I.

X-^>P 774412 transfer the contents of X into A, skip if the

previous A is positive.

SAM 771201 skip if A plus one is ?7777 Tv Note that -iif^

-tw-e^-s-c^^B ^lcmcnt m o dtr f this will skip only if
A contains -2. -^Ef^— e no * s mod© ^ — this liibti ' tact ion

The follov/ing are different in One's and Two's Mode.

One' s Mode

symbolic octal

A4-I<P 773606

A+I<P| 773611

A+K2 773633

NXP

action

skip if the sum of A and I is < -0 or =iO.

skip if the sum of A and I is not (< -0 or

skip

=to).

the sum of A and I is put into Z. If the sum
was > -0^ the instruction will skip.

776202 skip if X is 777777.

Two' s Mode

A+I<P

if-r f^"

-t-

A+I<P|
A+IX>

NXP

773607 skip if the sum of A and I is ;^ 0.

77j610 skip if the sum of A and I is > 0.

773632 the sum of A and I is put into X. If the sum
is •> 0;, the Instruction will skip.

776202

skip is X is 0.

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